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ON Semiconductor 
MC10H131PG的详细信息
| Manufacturer： | ON Semiconductor |
|---|---|
| Product Category： | Flip Flops |
| RoHS： | Yes |
| Brand： | ON Semiconductor |
| Number of Circuits： | 2 |
| Logic Family： | 10 |
| Logic Type： | Flip-Flop |
| Polarity： | Inverting/Non-Inverting |
| Input Type： | Single-Ended |
| Output Type： | Differential |
| Propagation Delay Time： | 1.7 ns |
| Supply Voltage - Max： | - 5.46 V |
| Maximum Operating Temperature： | + 75 C |
| Mounting Style： | Through Hole |
| Package / Case： | PDIP-16 |
| Packaging： | Tube |
| Minimum Operating Temperature： | 0 C |
| Number of Input Lines： | 2 |
| Number of Output Lines： | 2 |
| Series： | MC10H131 |
| Factory Pack Quantity： | 25 |
| Supply Voltage - Min： | - 4.94 V |
MC10H131PG相关文档
- Package Drawing: 20 LEAD PLLC
- Application Note: Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks
- Application Note: Clock Generation and Clock and Data Marking and Ordering Information Guide
- Application Note: AC Characteristics of ECL Devices
- Package Drawing: Ceramic DIP 16-Lead
- Application Note: The ECL Translator Guide
- Package Drawing: SOEIAJ-16
- Application Note: Metastability and the ECLinPS Family
- Application Note: Thermal Analysis and Reliability of WIRE BONDED ECL
- Application Note: Family Characteristics for MECL 10H™ and MECL 10K™
- Application Note: Using Wire-OR Ties in ECLInPS Designs
- Application Note: Designing with PECL (ECL at +5.0 V)
- Application Note: Phase Lock Loop General Operations
- Application Note: Storage and Handling of Drypack Surface Mount Device
- Package Drawing: PDIP-16
- Application Note: Interfacing Between LVDS and ECL
- Simulation Model: IBIS Model for MC10H131L
- Application Note: Termination of ECL Logic Devices
- Application Note: ECL Clock Distribution Techniques
- Application Note: Interfacing with ECLinPS™
- Application Note: ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide
- Simulation Model: MECL 10H SPICE Kit for Berkeley SPICE (PSPICE)
- Application Note: Clock Management Design Using Low Skew and Low Jitter Devices
- PCN: Qualification of JCET Chuzhou for PDIP (8-16 lead) package Assembly
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