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| 型号： | MC100EP16FDR2G |
| 厂商： |
 ON Semiconductor |
| 标准： |   |
| 分类： | 半导体 ， 集成电路 - IC |
| 描述： | bus transceivers 3.3V/5V ecl diff |
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Datasheet下载地址
| 本地下载 >> 厂商下载2 >> 第三方平台下载 >> |
MC100EP16FDR2G的详细信息
| Manufacturer： | ON Semiconductor |
|---|---|
| Product Category： | Bus Transceivers |
| RoHS： | Yes |
| Brand： | ON Semiconductor |
| Logic Type： | ECL Differential Receiver and Driver |
| Logic Family： | 100EP |
| Supply Voltage - Max： | +/- 5.5 V |
| Supply Voltage - Min： | +/- 3 V |
| Maximum Operating Temperature： | + 85 C |
| Package / Case： | SOIC-8 |
| Packaging： | Reel |
| Function： | Line Transmitter / Receiver |
| Minimum Operating Temperature： | - 40 C |
| Mounting Style： | SMD/SMT |
| Series： | MC100EP16F |
| Factory Pack Quantity： | 2500 |
MC100EP16FDR2G相关文档
- Application Note: Interfacing Between LVDS and ECL
- Application Note: AC Characteristics of ECL Devices
- Application Note: ECLinPS Plus™ Spice Modeling Kit
- Application Note: ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide
- Application Note: Interfacing with ECLinPS™
- Application Note: The ECL Translator Guide
- Application Note: Storage and Handling of Drypack Surface Mount Device
- Simulation Model: IBIS Model for mc100ep16dt 5.0V
- Application Note: Thermal Analysis and Reliability of WIRE BONDED ECL
- Simulation Model: IBS Model for MC100EP16DT 3.3V
- Application Note: Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks
- Application Note: Clock Generation and Clock and Data Marking and Ordering Information Guide
- Package Drawing: SOIC-8 Narrow Body
- Application Note: ECL Clock Distribution Techniques
- Simulation Model: IBIS Model for mc100ep16d 5.0V
- Application Note: Designing with PECL (ECL at +5.0 V)
- Application Note: Termination of ECL Logic Devices
- Application Note: Using Wire-OR Ties in ECLInPS Designs
- Application Note: Metastability and the ECLinPS Family
- Application Note: Phase Lock Loop General Operations
- Package Drawing: TSSOP 8 3.0x3.0x0.95 mm
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