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ON Semiconductor 
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MC100EL12DR2G的详细信息
| Manufacturer： | ON Semiconductor |
|---|---|
| Product Category： | Logic Gates |
| RoHS： | Yes |
| Brand： | ON Semiconductor |
| Product： | MUX Gates |
| Logic Family： | 100E |
| Number of Gates： | 1 |
| Number of Input Lines： | 2 |
| Number of Output Lines： | 4 |
| High Level Output Current： | - 50 mA |
| Low Level Output Current： | 50 mA |
| Propagation Delay Time： | 0.45 ns |
| Supply Voltage - Max： | +/- 5.7 V |
| Supply Voltage - Min： | +/- 4.2 V |
| Maximum Operating Temperature： | + 85 C |
| Mounting Style： | SMD/SMT |
| Package / Case： | SOIC-8 |
| Packaging： | Reel |
| Minimum Operating Temperature： | - 40 C |
| Number of Lines In/Out： | 2 / 4 |
| Series： | MC100EL12 |
| Factory Pack Quantity： | 2500 |
| Part # Aliases： | MC100EL12DG |
MC100EL12DR2G相关文档
- Simulation Model: IBIS Model for MC100EL12D VEE -5.2 V
- Application Note: AC Characteristics of ECL Devices
- Application Note: Designing with PECL (ECL at +5.0 V)
- Application Note: Phase Lock Loop General Operations
- Simulation Model: IBIS Model for MC100EL12DPECL - Positive ECL
- Package Drawing: TSSOP 8 3.0x3.0x0.95 mm
- Application Note: Termination of ECL Logic Devices
- Application Note: Interfacing with ECLinPS™
- Application Note: ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit
- Application Note: The ECL Translator Guide
- Application Note: Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks
- Application Note: Metastability and the ECLinPS Family
- Package Drawing: SOIC-8 Narrow Body
- Application Note: Clock Management Design Using Low Skew and Low Jitter Devices
- Application Note: Thermal Analysis and Reliability of WIRE BONDED ECL
- Application Note: Storage and Handling of Drypack Surface Mount Device
- Application Note: ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide
- Application Note: Clock Generation and Clock and Data Marking and Ordering Information Guide
- Application Note: ECL Clock Distribution Techniques
- Application Note: Interfacing Between LVDS and ECL
- Application Note: Using Wire-OR Ties in ECLInPS Designs
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